The disclosure relates to the display of images, such as by using display panels.
FIG. 1 is a schematic diagram of a display device. Gate driver 10 outputs the scan signals (also referred to as scan pulses) of each of the gate lines G1, G2, . . . , Gn according to a predetermined sequence. When a scan signal is carried on one gate line, the thin film transistors (TFTs) within all display units 200 on the same row or “scan line” are turned on while the TFTs within all display units 200 on rows or other scan lines are in a state to be turned off. When a scan line is selected, data or source driver 20 outputs a video signal (gray value) to the m display units of the respective rows through source lines S1, S2, . . . , Sm according to the image data to be displayed. After gate driver 10 scans n rows continuously, the display of a single frame is completed. Thus, repeated scans of each scan line can achieve the purpose of continuously displaying the image.
Typically, a video signal, which is transferred by the source lines S1, S2, . . . , Sm, is divided into a positive video signal and a negative video signal based on the relationship with the common electrode voltage VCOM. The positive video signal indicates a signal having a voltage level higher than the voltage VCOM. On the other hand, the negative video signal indicates a signal having a voltage level lower than the voltage VCOM. When a positive video signal and a negative video signal are individually applied to the display units 200, the display effect generally is the same.
In order to prevent the liquid crystal molecules of a display unit from continuously receiving a single-polar bias voltage, which reduces the liquid crystal molecular life, a display unit respectively receives positive and negative polar video signals corresponding to odd and even frames.
The disposition of the different polar video signals in each display unit can be divided into frame inversion, column inversion, and dot inversion. In frame inversion driving mode, the polarity of the video signals are the same for all display units during the same frame, but the opposite polarity is used for all displays during adjacent frames.
FIG. 2a is a schematic diagram of a column inversion driving mode. The display units of the same column on the same frame use the same polarity of the video signal, but the opposite polarity of the video signal is used for display units of adjacent lines or columns. For example, when gate driver 10 asserts gate line G1, controller 25 turns on switch SW21a and data driver 21 provides data signal D1 of a positive voltage to source line S1. Next, controller 25 turns on switch SW21b and data driver 21 provides data signal D1 of a negative voltage to source line S2. Then, controller 25 turns on switch SW21c and data driver 21 provides data signal D1 of a positive voltage to source line S3.
When gate driver 10 asserts gate line G2, controller 25 turns on switch SW21a and data driver 21 provides data signal D1 of a positive voltage to source line S1. Next, controller 25 turns on switch SW21b and data driver 21 provides data signal D1 of a negative voltage to source line S2. Then, controller 25 turns on switch SW21c and data driver 21 provides data signal D1 of a positive voltage to source line S3. Note that the operation of data drivers 22-24 is similar to that of data driver 21.
In this example, the polarity of the data signal D1 provided from data driver 21 is changed twice per line. Assuming the resolution of the display panel is 240×3×320 and a frame frequency is 60 Hz, a switch frequency of data driver 21 is 38.4 KHz (60 Hz×320×2).
FIG. 2b is a schematic diagram of a dot inversion driving mode. In dot inversion driving mode, the polarity of the video signals used by the display units during the same frame is presented in an interlaced form.
For example, when gate driver 10 asserts gate line G1, controller 25 turns on switch SW21a and data driver 21 provides data signal D1 of a positive voltage to source line S1. Next, controller 25 turns on switch SW21b and data driver 21 provides data signal D1 of a negative voltage to source line S2. Then, controller 25 turns on switch SW21c and data driver 21 provides data signal D1 of a positive voltage to source line S3.
When gate driver 10 asserts gate line G2, controller 25 turns on switch SW21a and data driver 21 provides data signal D1 of a negative voltage to source line S1. Next, controller 25 turns on switch SW21b and data driver 21 provides data signal D1 of a positive voltage to source line S2. Then, controller 25 turns on switch SW21c and data driver 21 provides data signal D1 of a negative voltage to source line S3.
In this example, the polarity of voltage provided from data driver 21 is changed three times per line. That is, in contrast to the column inversion driving mode, the polarity of the signal D1 changes a third time for each gate line because the signal D1 changes polarity between the last source line of a respective gate line and the first source line of the next gate line, e.g., between G1-S3 and G2-S1. Assuming the resolution of the display panel is 240×3×320 and a frame frequency is 60 Hz, a switch frequency of data driver 21 is 57.6 KHz (60 Hz×320×3).